The convergence of Quantum with AI
Qubits built from superconducting circuits cooled to near absolute zero. The most industrially mature approach, favoured by IBM, Google, and Rigetti; fast gates, but short coherence times and demanding cryogenics.
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D-Wave has been awarded up to $100 million through the U.S. CHIPS Act to expand its quantum computing hardware efforts. The funding supports its dual-platform strategy, covering both quantum annealing and gate-model systems.
D-Wave could use the federal funding to bring a gate-model processor to its Leap cloud service within two years, giving existing annealing customers an on-ramp to circuit-model workloads.
NEC Corporation has ended its research and development of superconducting quantum computers. The company will shift toward quantum-inspired annealing and classical emulation, concentrating on software and optimization services. Fujitsu remains the main Japanese corporate developer of superconducting quantum hardware.
NEC could package its annealing and classical emulation capabilities into commercial optimization services for Japanese enterprises within the next two years.
A preprint on arXiv reports a study applying quantum graph neural networks to jet classification, motivated by jet measurements at the Large Hadron Collider and the future Electron-Ion Collider. The authors explore quantum machine learning methods for jet tagging and present an implementation intended to run on quantum hardware.
This preprint could become a reference benchmark for quantum GNN jet tagging on small datasets, with follow-up papers testing variations in encoding and circuit depth across cloud-accessible quantum processors.
A new preprint describes TETRIS-Q, a tiling-based technique intended to reduce transient faults in superconducting qubits caused by external radiation. It positions radiation-induced errors as a remaining challenge even amid progress in quantum error correction. The abstract introduces the method but does not report experimental validation in the available excerpt.
If the tiling scheme can be applied to existing interleaved superconducting qubit layouts, it could within two years be integrated into quantum error correction experiments to reduce radiation-induced correlated errors without new hardware.
A new benchmarking study tests whether surface-code decoder rankings derived from simulated noise models hold on real quantum hardware. It uses Google's Willow processor, a device that has operated below the surface-code error-correction threshold, as the hardware testbed.
If decoder rankings transfer from simulation to Willow-class hardware, error-correction teams could select and optimise surface-code decoders largely in simulation, reducing the need for repeated on-device benchmarking during early logical qubit experiments.
NEC has decided to halt development of quantum computer hardware, according to The Quantum Insider. The move shifts NEC away from building its own quantum computer systems.
NEC could pivot to quantum software, integration, and managed services, using third-party quantum hardware to serve its existing enterprise customers.
IBM has made its Nighthawk r2 processor available on the IBM Quantum Platform. The 120-qubit device introduces a qubit-reset architecture that IBM reports delivers up to 25 times the circuit throughput of its Heron systems, exceeding 100,000 circuits per second.
This throughput increase could make practical quantum error mitigation techniques that require large numbers of circuit executions, improving the quality of results on Nighthawk r2 for chemistry and optimization workloads within the next two years.
IBM Quantum announced a new superconducting processor, Nighthawk r2, with 120 programmable qubits. The company reports that it executes circuits 25 times faster than its previous Heron-generation processors. The processor is positioned for quantum error correction work.
The faster circuit execution could allow IBM to run deeper, more frequent error-correction cycles within the next two years, making it feasible to demonstrate repeated stabilizer measurements and logical qubit performance on Nighthawk r2.
George Mason University has entered a strategic hardware partnership with Oxford-based quantum infrastructure firm TreQ to deploy an open-architecture quantum computer at its Northern Virginia campus. The $7.7 million system is backed by catalytic funding from the Virginia Innovation Partnership Corporation and university capital.
GMU's open-architecture QPU could become a regional testbed where Virginia-based defense and technology firms evaluate modular quantum hardware without owning their own systems, shortening integration cycles for hybrid classical-quantum workloads.
Rigetti Computing and Purdue University have published joint research extending Rigetti's quantum preconditioning framework to hard-constrained combinatorial optimization problems. The method uses two-point variable correlations extracted from shallow QAOA circuits to modify the problem's objective function before it is passed to a classical solver.
Within two years, this framework could become a standard preprocessing step in Rigetti's cloud service, letting users submit constrained optimization problems, receive QAOA-derived correlation data, and warm-start commercial classical solvers.
Qilimanjaro reported a machine learning readout with 99.9% accuracy in quantum reservoir computing experiments. The approach trains only the readout layer, leaving the quantum reservoir itself untrained, and is positioned as a response to rising classical ML training costs.
If 99.9% readout accuracy holds outside controlled experiments, Qilimanjaro's superconducting reservoir hardware could become a practical near-term platform for low-overhead time-series forecasting, such as energy demand or sensor prediction.
A preprint describes a microwave-free approach to preparing and measuring the state of superconducting qubits. It targets the calibrated microwave signals and roughly 100 ns measurement times that the authors identify as obstacles to scaling superconducting quantum processors.
If the method's fidelity and speed hold up outside the lab, it could be folded into cryogenic control stacks for multi-qubit superconducting processors within two years, reducing per-qubit microwave calibration overhead.
A new arXiv preprint addresses fault-tolerant quantum computation using bosonic qubits, focusing on dual-rail and cat encodings together with bias-preserving gates. The authors frame the problem around the need for universal logical operations, suppression of hardware-specific noise, and efficient handling of photon-loss errors, noting that each encoding alone has attractive features but also important limitations.
If the proposed dual-rail cat code construction can be implemented in existing superconducting cavity or photonic platforms, it could enable near-term experiments demonstrating bias-preserving gates and error correction that simultaneously address photon loss and hardware noise.
Researchers propose a hierarchical quantum error correction scheme that concatenates hypergraph product codes as an outer layer with rotated surface codes as an inner layer. The design is compatible with quantum processors limited to nearest-neighbor interactions. The outer code uses (3,4)-random HGP codes, which are known for their constant encoding rate.
This hierarchical scheme could become a benchmark for fault-tolerant circuit simulations on nearest-neighbor hardware, guiding which code families to prioritize for early logical qubit demonstrations.
A preprint on arXiv describes an FPGA-based machine-learning classifier designed to identify superconducting qubit states in real time. The work targets mid-circuit measurement and conditional feed-forward, framing current superconducting readout as both latency-bound and error-prone compared with classical transistor-level state detection. The abstract stops short of reporting full system-level benchmarks, presenting the integration as a response to that readout gap.
If the FPGA implementation validates on current superconducting hardware with multi-qubit readout, it could be integrated into existing control stacks as a drop-in discriminator for MCM loops within two years.
Researchers released the data and code accompanying a study of collision-model preparation of Dicke states. The work reports depth–fidelity trade-offs, circuit resource costs, and measurements taken on superconducting quantum processors. Dicke states are multipartite entangled states with a fixed number of excitations shared across qubits, relevant to quantum sensing and networking.
The released code and measured baselines could let other groups test whether collision-model Dicke-state circuits reduce depth enough to become a standard preparation route for fixed-excitation sensing states on noisy superconducting processors.
A preprint studies superconducting quantum error correction for qLDPC codes with nonlocal stabilizers. It examines how an enriched native two-qubit gate set — CNOT plus CXSWAP — can simplify syndrome extraction circuits. The work, titled 'Bunny Codes,' presents an exhaustive analysis of these gate-set advantages.
Superconducting hardware teams could adopt CXSWAP as a native gate within two years, enabling small qLDPC codes with nonlocal stabilizers to be tested on existing fixed-connectivity processors without costly SWAP decompositions.
Researchers experimentally evaluated a combination of error mitigation and finite-shot sampling techniques on an IBM Quantum superconducting processor under a constrained execution budget. The methods included calibration-aware qubit selection, circuit-depth scaling, zero-noise extrapolation, dynamical decoupling, readout-error mitigation, and repeated-shot estimation. The work focuses on hardware-efficient error mitigation and shot-efficient sampling rather than full error correction.
If the combined calibration-aware qubit selection and layered error mitigation generalizes beyond the studied circuits, this could become a default execution mode in Qiskit Runtime within two years, reducing the shot and depth cost of running noise-sensitive algorithms on IBM Quantum processors.
Researchers report superconducting microwave resonators that incorporate aluminium-indium arsenide (Al-InAs) weak links and exhibit both cubic nonlinearity for three-wave mixing and quartic Kerr nonlinearity. The work examines these nonlinearities in the context of parametric amplification and continuous-variable quantum information tasks, noting that quartic contributions can limit device performance.
Within two years, these Al-InAs weak-link resonators could be engineered to suppress the quartic Kerr term enough to serve as on-chip three-wave mixing elements for Josephson parametric amplifiers or continuous-variable entanglement sources.
A research team used IBM quantum hardware to test a drug-docking method, as reported by The Quantum Insider. The work focuses on molecular docking calculations used in drug discovery. The available abstract does not include specific performance or accuracy results.
Pharmaceutical research groups could begin benchmarking this quantum drug-docking method against classical docking tools on IBM's cloud-accessible superconducting processors within two years.